Is this a factory mod?

[cheshirenoir]

Trying to repair a 700305H revision motherboard that has been "attacked" by the previous owner.
So far I have replaced the track they lifted near the power supply connector, desoldered and resoldered properly the power connector itself and cleaned up a burn mark near the crystal.
This I don't know what these two wires are. They don't look nearly as rough as the other soldering so I was wondering if they were "factory"?

IMG20230311183359.jpg

Can anyone help me?

(BTW fault is that the whole system seems to be halted. Address lines are all held high and data lines aren't doing much either.)

Cheers!

John

[Scouter3d]

Hi Chesh,

Wow, my 305F Version has even more cut traces and patchwires... :0)

I would check:
6502 Pin 40 for /RESET
6502 Pin 37 for PHI0

You can also check using the MegaSDCart (As it replaces the internal BIOS ROM)

If there is no movement on the Addresslines (despite PHI0 frequency OK and /RESET OK) i would suspect the 6502 to be faulty...

Cheers, TOM:0)

20230311_142321_bigger.jpg

20230311_142307_bigger.jpg

[cheshirenoir]

Thanks for that Tom,

PHI0 has a 2MHz clock,
RESET is going HIGH after a short delay. Presumably that's all "sane"...

I guess I'll need to pull the 6502 and look for a spare... I'll check if the one in my Apple is socketed...

John

[Scouter3d]

Small correction: My board REV. is 305 F
Cheers, TOM:0)

[cheshirenoir]

OK so I have swapped over the 6502 into my Apple IIe and it boots fine, so it's not the CPU.
(I also tried it with the MegaSDCart, with no change)
Looking at the schematic, there's a lot of things hanging off that data bus and, of course, none of them are in sockets :-/

What's the startup order for the CreatiVision? I assume there's a boot vector in the onboard ROM? I assume C109 and R66 are there to hold the reset line low for a moment?

I have no idea what to do next

John

[Scouter3d]

Oh no, it would have been too easy :0)

Yes, there is a boot vector in the ROM and yes, C109 and R66 are for RESET...

Most of the components are connected to the Data lines, now it would be interesting at what address the CV stops working
Are the Data- and Address-lines "stuck" or is there at least a bit of movement at startup?

My next candidates would be: 2114 RAMs, I/O Chip 6821, TMS9929 but without more info it could be anything (like the 74LS139)
I would rule out: the 8x 4116 RAMs (as they mostly produce graphic-glitches when defect) and the ROM (If it not completely shortend the BUS)

You can try Piggybacking the 2214s with working chips, this sometimes works...

Good Luck finding the fault!

Cheers, TOM:0)

[@username@]

The 6502 just jumps to the vector at $FFFC and executes from there.

There are a couple of code areas at initialisation which could sit in a loop forever and they are tied to the PIA.

For example, to silence the PSG, the logic is place byte on bus and wait for acknowledge.

Code: Select all

 fe77 8d 02 10        STA        DAT_1002
 fe7a ad 03 10        LDA        DAT_1003
 fe7d 10 fb           BPL        LAB_fe7a
 fe7f ad 02 10        LDA        DAT_1002
 fe82 60              RTS

So write to PIA (MMIO 1002 - PSG DATA) then wait for MSB to be set on MMIO 1003 PSG ACKNOWLEDGE. If the MSB is never set then the system will just turtle.

The PIA is also used for keyboard polling later when IRQs are enabled - but the logo should be on screen by then.

Good luck!

[cheshirenoir]

When I checked, all address lines seemed to be stuck at high, so presumably FFFF.
This could be the excuse to get a logic analyser I have been looking for

John

[Scouter3d]

Yes ;0)

i have the smallest, cheapest chinese one and even that is a great help :0)

Cheers, TOM:0)

[Scouter3d]

Hi @username@, I fried several PIAs during the CVKey developement so yes, it could be a good candidate...